mc68hc908qf4 Freescale Semiconductor, Inc, mc68hc908qf4 Datasheet - Page 125

• Manufacturer Part Number: mc68hc908qf4
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

14.4.2.3 Illegal Opcode Reset
14.4.2.4 Illegal Address Reset
14.4.2.5 Low-Voltage Inhibit (LVI) Reset
MC68HC908QF4 — Rev. 1.0
MOTOROLA
ADDRESS BUS
BUSCLKX4
BUSCLKX2
PORRST
OSC1
RST
The SIM decodes signals from the CPU to detect illegal instructions. An illegal
instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a
reset.
If the stop enable bit, STOP, in the mask option register is 0, the SIM treats the
STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM
actively pulls down the RST pin for all internal reset sources.
An opcode fetch from an unmapped address generates an illegal address reset.
The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit
in the SIM reset status register (SRSR) and resetting the MCU. A data fetch from
an unmapped address does not generate a reset. The SIM actively pulls down the
RST pin for all internal reset sources. See
ranges.
The LVI asserts its output to the SIM when the V
voltage V
external reset pin (RST) is held low while the SIM counter counts out 4096
BUSCLKX4 cycles after V
later, the CPU and memories are released from reset to allow the reset vector
sequence to occur. The SIM actively pulls down the (RST) pin for all internal reset
sources.
CYCLES
Freescale Semiconductor, Inc.
4096
For More Information On This Product,
TRIPF
(RST PIN IS A GENERAL-PURPOSE INPUT AFTER A POR)
. The LVI bit in the SIM reset status register (SRSR) is set, and the
Figure 14-7. POR Recovery
System Integration Module (SIM)
CYCLES
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32
DD
CYCLES
32
rises above V
Figure 2-1. Memory Map
TRIPR
. Sixty-four BUSCLKX4 cycles
DD
$FFFE
System Integration Module (SIM)
voltage falls to the LVI trip
Reset and System Initialization
$FFFF
for memory
Data Sheet
125