mc68hc908qf4 Freescale Semiconductor, Inc, mc68hc908qf4 Datasheet - Page 57

• Manufacturer Part Number: mc68hc908qf4
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

6.3.6 COPD (COP Disable)
6.3.7 COPRS (COP Rate Select)
6.4 COP Control Register
6.5 Interrupts
6.6 Monitor Mode
6.7 Low-Power Modes
6.7.1 Wait Mode
MC68HC908QF4 — Rev. 1.0
MOTOROLA
The COPD signal reflects the state of the COP disable bit (COPD) in the
configuration register (CONFIG). See
(CONFIG).
The COPRS signal reflects the state of the COP rate select bit (COPRS) in the
configuration register 1 (CONFIG1). See
(CONFIG).
The COP control register (COPCTL) is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and starts a new
timeout period. Reading location $FFFF returns the low byte of the reset vector.
The COP does not generate CPU interrupt requests.
The COP is disabled in monitor mode when V
The WAIT and STOP instructions put the MCU in low power-consumption standby
modes.
The COP continues to operate during wait mode. To prevent a COP reset during
wait mode, periodically clear the COP counter.
Address: $FFFF
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
For More Information On This Product,
Bit 7
Computer Operating Properly (COP)
Go to: www.freescale.com
Figure 6-2. COP Control Register (COPCTL)
6
5
LOW BYTE OF RESET VECTOR
CLEAR COP COUNTER
Section 5. Configuration Register
Unaffected by reset
4
Section 5. Configuration Register
TST
Computer Operating Properly (COP)
3
is present on the IRQ pin.
2
COP Control Register
1
Data Sheet
Bit 0
57