mc68hc908qf4 Freescale Semiconductor, Inc, mc68hc908qf4 Datasheet - Page 75

• Manufacturer Part Number: mc68hc908qf4
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

MC68HC908QF4 — Rev. 1.0
MOTOROLA
$001D
Addr.
IRQPUD
IRQ
IRQ Status and Control
Register Name
NOTE:
Register (INTSCR)
DECODER
VECTOR
RESET
FETCH
ACK
V
See page 77.
DD
INTERNAL
PULLUP
DEVICE
When the interrupt pin is both falling-edge and low-level triggered (MODE = 1), the
CPU interrupt request remains set until both of the following occur:
The vector fetch or software clear may occur before or after the interrupt pin returns
to logic 1. As long as the pin is low, the interrupt request remains pending. A reset
will clear the latch and the MODE control bit, thereby clearing the interrupt even if
the pin stays low.
When set, the IMASK bit in the INTSCR mask all external interrupt requests. A
latched interrupt request is not presented to the interrupt priority logic unless the
IMASK bit is clear.
The interrupt mask (I) in the condition code register (CCR) masks all interrupt
requests, including external interrupt requests. See
Figure 8-3
•
•
Reset:
Read:
Write:
Vector fetch or software clear
Return of the interrupt pin to logic 1
Freescale Semiconductor, Inc.
V
MODE
Figure 8-2. IRQ Module Block Diagram
For More Information On This Product,
Figure 8-3. IRQ I/O Register Summary
DD
provides a summary of the IRQ I/O register.
D
Bit 7
CK
0
0
CLR
IRQ
FF
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Q
= Unimplemented
External Interrupt (IRQ)
6
0
0
5
0
0
IMASK
SYNCHRO-
VOLTAGE
DETECT
4
0
0
NIZER
HIGH
IRQF
3
0
14.6 Exception
ACK
IRQF
2
0
0
External Interrupt (IRQ)
Functional Description
IMASK
1
0
Control.
TO CPU FOR
BIL/BIH
INSTRUCTIONS
IRQ
INTERRUPT
REQUEST
TO MODE
SELECT
LOGIC
Data Sheet
MODE
Bit 0
0
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