mc68hc908qf4 Freescale Semiconductor, Inc, mc68hc908qf4 Datasheet - Page 44

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mc68hc908qf4

Manufacturer Part Number
mc68hc908qf4
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Analog-to-Digital Converter (ADC)
3.7.3 ADC Input Clock Register
Data Sheet
44
This register selects the clock frequency for the ADC.
ADIV2–ADIV0 — ADC Clock Prescaler Bits
Address: $003F
Reset:
Read:
Write:
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used
by the ADC to generate the internal ADC clock.
clock configurations. The ADC clock should be set according to the MCU
operating voltage. Lower operating voltages will require lower ADC clock
frequencies for best accuracy. The analog input level should remain stable for
the entire conversion time (maximum = 17 ADC clock cycles).
Freescale Semiconductor, Inc.
ADIV2
For More Information On This Product,
Bit 7
0
Figure 3-6. ADC Input Clock Register (ADICLK)
X = don’t care
ADIV2
Analog-to-Digital Converter (ADC)
0
0
0
0
1
= Unimplemented
Go to: www.freescale.com
ADIV1
6
0
Table 3-2. ADC Clock Divide Ratio
ADIV1
ADIV0
X
0
0
1
1
5
0
4
0
0
ADIV0
X
0
1
0
1
3
0
0
Table 3-2
ADC Clock Rate
Bus clock ÷ 16
Bus clock ÷ 1
Bus clock ÷ 2
Bus clock ÷ 4
Bus clock ÷ 8
2
0
0
MC68HC908QF4 — Rev. 1.0
shows the available
1
0
0
MOTOROLA
Bit 0
0
0

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