mc68hc908qf4 Freescale Semiconductor, Inc, mc68hc908qf4 Datasheet - Page 88

• Manufacturer Part Number: mc68hc908qf4
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Low-Voltage Inhibit (LVI)
10.3.1 Polled LVI Operation
10.3.2 Forced Reset Operation
10.3.3 Voltage Hysteresis Protection
Data Sheet
88
NOTE:
The LVI is enabled out of reset. The LVI module contains a bandgap reference
circuit and comparator. Clearing the LVI power disable bit (LVIPWRD) enables the
LVI to monitor V
the LVI module to generate a reset when V
V
operate in stop mode. Setting the LVD or LVR trip point bit (LVDLVR) selects the
LVD trip point voltage. The actual trip thresholds are specified in
Electrical
After a power-on reset, the LVI’s default mode of operation is LVR trip voltage. If a
higher trip voltage is desired, the user must set the LVDLVR bit to raise the trip
point to the LVD voltage.
If the user requires the higher trip voltage and sets the LVDLVR bit after power-on
reset while the VDD supply is not above the V
microcontroller unit (MCU) will immediately go into reset. The next time the LVI
releases the reset, the supply will be above the V
Once an LVI reset occurs, the MCU remains in reset until V
voltage, V
Integration Module (SIM)
The output of the comparator controls the state of the LVIOUT flag in the LVI status
register (LVISR) and can be used for polling LVI operation when the LVI reset is
disabled.
In applications that can operate at V
monitor V
bit must be cleared to enable the LVI module, and the LVIRSTD bit must be set to
disable LVI resets.
In applications that require V
resets allows the LVI module to reset the MCU when V
level. In the configuration register, the LVIPWRD and LVIRSTD bits must be
cleared to enable the LVI module and to enable LVI resets.
Once the LVI has triggered (by having V
a reset condition until V
prevents a condition in which the MCU is continually entering and exiting reset if
V
hysteresis voltage, V
DTRIPF
DD
is approximately equal to V
Freescale Semiconductor, Inc.
. Setting the LVI enable in stop mode bit (LVISTOP) enables the LVI to
For More Information On This Product,
DD
TRIPR
Characteristics. Either trip level can be used as a detect or reset.
by polling the LVIOUT bit. In the configuration register, the LVIPWRD
, which causes the MCU to exit reset. See
DD
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voltage. Clearing the LVI reset disable bit (LVIRSTD) enables
Low-Voltage Inhibit (LVI)
HYS
DD
.
rises above the rising trip point voltage, V
for the reset recovery sequence.
DD
to remain above the V
TRIPF
DD
. V
levels below the V
DD
TRIPR
fall below V
DD
TRIPR
is greater than V
falls below a voltage, V
TRIPR
for LVD mode, the
TRIPF
TRIPF
DD
for LVD mode.
TRIPF
MC68HC908QF4 — Rev. 1.0
falls below the V
Section 14. System
DD
), the LVI will maintain
level, enabling LVI
level, software can
rises above a
TRIPF
17.5 DC
TRIPR
by the
TRIPF
MOTOROLA
. This
TRIPF
or