mc68hc908qf4 Freescale Semiconductor, Inc, mc68hc908qf4 Datasheet - Page 128

• Manufacturer Part Number: mc68hc908qf4
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

System Integration Module (SIM)
14.6.1.1 Hardware Interrupts
Data Sheet
128
ADDRESS BUS
ADDRESS BUS
INTERRUPT
INTERRUPT
DATA BUS
DATA BUS
MODULE
MODULE
I BIT
I BIT
R/W
R/W
DUMMY
Interrupts are latched, and arbitration is performed in the SIM at the start of
interrupt processing. The arbitration result is a constant that the CPU uses to
determine which vector to fetch. Once an interrupt is latched by the SIM, no other
interrupt can take precedence, regardless of priority, until the latched interrupt is
serviced (or the I bit is cleared).
At the beginning of an interrupt, the CPU saves the CPU register contents on the
stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end
of an interrupt, the RTI instruction recovers the CPU register contents from the
stack so that normal processing can resume.
timing.
A hardware interrupt does not stop the current instruction. Processing of a
hardware interrupt begins after completion of the current instruction. When the
current instruction is complete, the SIM checks all pending hardware interrupts. If
interrupts are not masked (I bit clear in the condition code register), and if the
corresponding interrupt enable bit is set, the SIM proceeds with interrupt
processing; otherwise, the next instruction is fetched and executed.
DUMMY
Freescale Semiconductor, Inc.
SP – 4
Figure 14-10
SP
For More Information On This Product,
PC – 1[7:0] PC – 1[15:8]
CCR
Figure 14-10. Interrupt Recovery
SP – 1
SP – 3
Figure 14-9
System Integration Module (SIM)
Go to: www.freescale.com
A
shows interrupt recovery timing.
SP – 2
SP – 2
.
X
Interrupt Entry
X
SP – 3
SP – 1
PC – 1[7:0] PC – 1[15:8] OPCODE
A
SP – 4
SP
CCR
Figure 14-9
VECT H
PC
V DATA H
VECT L
PC + 1
MC68HC908QF4 — Rev. 1.0
shows interrupt entry
OPERAND
V DATA L
START ADDR
OPCODE
MOTOROLA