mc68hc908qf4 Freescale Semiconductor, Inc, mc68hc908qf4 Datasheet - Page 144

• Manufacturer Part Number: mc68hc908qf4
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Timer Interface Module (TIM)
15.4.4.2 Buffered PWM Signal Generation
15.4.4.3 PWM Initialization
Data Sheet
144
NOTE:
NOTE:
Channels 0 and 1 can be linked to form a buffered PWM channel whose output
appears on the TCH0 pin. The TIM channel registers of the linked pair alternately
control the pulse width of the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links
channel 0 and channel 1. The TIM channel 0 registers initially control the pulse
width on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM
channel 1 registers to synchronously control the pulse width at the beginning of the
next PWM period. At each subsequent overflow, the TIM channel registers (0 or 1)
that control the pulse width are the ones written to last. TSC0 controls and monitors
the buffered PWM function, and TIM channel 1 status and control register (TSC1)
is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a
general-purpose I/O pin.
In buffered PWM signal generation, do not write new pulse width values to the
currently active channel registers. User software should track the currently active
channel to prevent writing a new value to the active channel. Writing to the active
channel registers is the same as generating unbuffered PWM signals.
To ensure correct operation when generating unbuffered or buffered PWM signals,
use the following initialization procedure:
In PWM signal generation, do not program the PWM channel to toggle on output
compare. Toggling on output compare prevents reliable 0% duty cycle generation
and removes the ability of the channel to self-correct in the event of software error
1. In the TIM status and control register (TSC):
2. In the TIM counter modulo registers (TMODH:TMODL), write the value for
3. In the TIM channel x registers (TCHxH:TCHxL), write the value for the
4. In TIM channel x status and control register (TSCx):
the required PWM period.
required pulse width.
Freescale Semiconductor, Inc.
a. Stop the TIM counter by setting the TIM stop bit, TSTOP.
b. Reset the TIM counter and prescaler by setting the TIM reset bit,
a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (polarity 1 — to clear output on compare) or 1:1 (polarity 0 —
For More Information On This Product,
TRST.
buffered output compare or PWM signals) to the mode select bits,
MSxB:MSxA. See
to set output on compare) to the edge/level select bits, ELSxB:ELSxA.
The output action on compare must force the output to the complement
of the pulse width level. See
Go to: www.freescale.com
Timer Interface Module (TIM)
Table
15-3.
Table
15-3.
MC68HC908QF4 — Rev. 1.0
MOTOROLA