mc68hc908qf4 Freescale Semiconductor, Inc, mc68hc908qf4 Datasheet - Page 40

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mc68hc908qf4

Manufacturer Part Number
mc68hc908qf4
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Analog-to-Digital Converter (ADC)
3.3.1 ADC Port I/O Pins
3.3.2 Voltage Conversion
3.3.3 Conversion Time
3.3.4 Continuous Conversion
3.3.5 Accuracy and Precision
Data Sheet
40
NOTE:
PTA0, PTA1, PTA4, and PTA5 are general-purpose I/O pins that are shared with
the ADC channels. The channel select bits (ADC status and control register
(ADSCR), $003C), define which ADC channel/port pin will be used as the input
signal. The ADC overrides the port I/O logic by forcing that pin as input to the ADC.
The remaining ADC channels/port pins are controlled by the port I/O logic and can
be used as general-purpose I/O. Writes to the port register or data direction register
(DDR) will not have any affect on the port pin that is selected by the ADC. Read of
a port pin which is in use by the ADC will return a 0 if the corresponding DDR bit is
at 0. If the DDR bit is 1, the value in the port data latch is read.
When the input voltage to the ADC equals V
(full scale). If the input voltage equals V
voltages between V
voltages will result in $FF if greater than V
Input voltage should not exceed the analog supply voltages.
Sixteen ADC internal clocks are required to perform one conversion. The ADC
starts a conversion on the first rising edge of the ADC internal clock immediately
following a write to the ADSCR. If the ADC internal clock is selected to run at
1 MHz, then one conversion will take 16 µs to complete. With a 1-MHz ADC
internal clock the maximum sample rate is 62.5 kHz.
In the continuous conversion mode (ADCO = 1), the ADC continuously converts
the selected channel filling the ADC data register (ADR) with new data after each
conversion. Data from the previous conversion will be overwritten whether that
data has been read or not. Conversions will continue until the ADCO bit is cleared.
The COCO bit (ADSCR, $003C) is set after each conversion and will stay set until
the next read of the ADC data register.
When a conversion is in process and the ADSCR is written, the current conversion
data should be discarded to prevent an incorrect reading.
The conversion process is monotonic and has no missing codes.
Number of Bus Cycles = Conversion Time × Bus Frequency
Freescale Semiconductor, Inc.
For More Information On This Product,
Conversion Time =
Analog-to-Digital Converter (ADC)
Go to: www.freescale.com
DD
and V
ADC Clock Frequency
16 ADC Clock Cycles
SS
are a straight-line linear conversion. All other input
SS,
DD
the ADC converts it to $00. Input
DD
and $00 if less than V
, the ADC converts the signal to $FF
MC68HC908QF4 — Rev. 1.0
SS
.
MOTOROLA

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