mc68hc908qf4 Freescale Semiconductor, Inc, mc68hc908qf4 Datasheet - Page 76

• Manufacturer Part Number: mc68hc908qf4
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

External Interrupt (IRQ)
8.4 IRQ Pin
8.5 IRQ Module During Break Interrupts
Data Sheet
76
NOTE:
NOTE:
A falling edge on the IRQ pin can latch an interrupt request into the IRQ latch. A
vector fetch, software clear, or reset clears the IRQ latch.
If the MODE bit is set, the IRQ pin is both falling-edge sensitive and low-level
sensitive. With MODE set, both of the following actions must occur to clear IRQ:
The vector fetch or software clear and the return of the IRQ pin to logic 1 may occur
in any order. The interrupt request remains pending as long as the IRQ pin is at
logic 0. A reset will clear the latch and the MODE control bit, thereby clearing the
interrupt even if the pin stays low.
If the MODE bit is clear, the IRQ pin is falling-edge sensitive only. With MODE
clear, a vector fetch or software clear immediately clears the IRQ latch.
The IRQF bit in the INTSCR register can be used to check for pending interrupts.
The IRQF bit is not affected by the IMASK bit, which makes it useful in applications
where polling is preferred.
When the IRQ function is enabled in the CONFIG2 register, the BIH and BIL
instructions can be used to read the logic level on the IRQ pin. If the IRQ function
is disabled, these instructions will behave as if the IRQ pin is a logic 1, regardless
of the actual level on the pin. Conversely, when the IRQ function is enabled, bit 2
of the port A data register will always read a 0.
When using the level-sensitive interrupt trigger, avoid false interrupts by masking
interrupt requests in the interrupt routine. An internal pullup resistor to V
connected to the IRQ pin; this can be disabled by setting the IRQPUD bit in the
CONFIG2 register ($001E).
The system integration module (SIM) controls whether the IRQ latch can be
cleared during the break state. The BCFE bit in the break flag control register
(BFCR) enables software to clear the latches during the break state. See
Section 14. System Integration Module
•
•
Vector fetch or software clear — A vector fetch generates an interrupt
acknowledge signal to clear the latch. Software may generate the interrupt
acknowledge signal by writing a 1 to the ACK bit in the interrupt status and
control register (INTSCR). The ACK bit is useful in applications that poll the
IRQ pin and require software to clear the IRQ latch. Writing to the ACK bit
prior to leaving an interrupt service routine can also prevent spurious
interrupts due to noise. Setting ACK does not affect subsequent transitions
on the IRQ pin. A falling edge that occurs after writing to the ACK bit latches
another interrupt request. If the IRQ mask bit, IMASK, is clear, the CPU
loads the program counter with the vector address at locations $FFFA and
$FFFB.
Return of the IRQ pin to logic 1 — As long as the IRQ pin is at logic 0, IRQ
remains active.
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External Interrupt (IRQ)
(SIM).
MC68HC908QF4 — Rev. 1.0
MOTOROLA
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