mc68hc908qf4 Freescale Semiconductor, Inc, mc68hc908qf4 Datasheet - Page 71

• Manufacturer Part Number: mc68hc908qf4
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

7.8 Opcode Map
MC68HC908QF4 — Rev. 1.0
MOTOROLA
SWI
TAP
TAX
TPA
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP
TSX
TXA
TXS
WAIT
A
C
CCR
dd
dd rr
DD
DIR
DIX+
ee ff
EXT
ff
H
H
hh ll
I
ii
IMD
IMM
INH
IX
IX+
IX+D
IX1
IX1+
IX2
M
N
Source
Form
Accumulator
Carry/borrow bit
Condition code register
Direct address of operand
Direct to direct addressing mode
Direct addressing mode
Direct to indexed with post increment addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry bit
Index register high byte
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate source to direct destination addressing mode
Immediate addressing mode
Indexed, no offset addressing mode
Indexed, no offset, post increment addressing mode
Indexed with post increment to direct addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 8-bit offset, post increment addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative bit
Direct address of operand and relative offset of branch instruction
Immediate operand byte
Inherent addressing mode
Software Interrupt
Transfer A to CCR
Transfer A to X
Transfer CCR to A
Test for Negative or Zero
Transfer SP to H:X
Transfer X to A
Transfer H:X to SP
Enable Interrupts; Wait for Interrupt
Operation
See
Table 7-1. Instruction Set Summary (Sheet 7 of 7)
Table
Freescale Semiconductor, Inc.
For More Information On This Product,
7-2.
Go to: www.freescale.com
Central Processor Unit (CPU)
(A) – $00 or (X) – $00 or (M) – $00
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
I bit ← 0; Inhibit CPU clocking
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; I ← 1
(SP) ← (H:X) – 1
Description
H:X ← (SP) + 1
until interrupted
CCR ← (A)
A ← (CCR)
X ← (A)
A ← (X)
n
opr
PC
PCH
PCL
REL
rel
rr
SP1
SP2
SP
U
V
X
Z
&
|
⊕
( )
–( )
#
«
←
?
:
—
Any bit
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer, 8-bit offset addressing mode
Stack pointer 16-bit offset addressing mode
Stack pointer
Undefined
Overflow bit
Index register low byte
Zero bit
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Immediate value
Sign extend
Loaded with
If
Concatenated with
Set or cleared
Not affected
V H I N Z C
– – 1 – – – INH
– – – – – – INH
– – – – – – INH
0 – –
– – – – – – INH
– – – – – – INH
– – – – – – INH
– – 0 – – – INH
on CCR
Effect
Central Processor Unit (CPU)
–
INH
DIR
INH
INH
IX1
IX
SP1
9E6D
Opcode Map
3D
4D
5D
6D
7D
83
84
97
85
95
9F
94
8F
Data Sheet
dd
ff
ff
71
9
2
1
1
3
1
1
3
2
4
2
1
2
1