mc68hc908qf4 Freescale Semiconductor, Inc, mc68hc908qf4 Datasheet - Page 151

• Manufacturer Part Number: mc68hc908qf4
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

MC68HC908QF4 — Rev. 1.0
MOTOROLA
NOTE:
CHxIE — Channel x Interrupt Enable Bit
MSxB — Mode Select Bit B
MSxA — Mode Select Bit A
Before changing a channel function by writing to the MSxB or MSxA bit, set the
TSTOP and TRST bits in the TIM status and control register (TSC).
This read/write bit enables TIM CPU interrupt service requests on channel x.
Reset clears the CHxIE bit.
This read/write bit selects buffered output compare/PWM operation. MSxB
exists only in the TIM channel 0 status and control register.
Setting MS0B disables the channel 1 status and control register and reverts
TCH1 to general-purpose I/O.
Reset clears the MSxB bit.
When ELSxB:A ≠ 00, this read/write bit selects either input capture operation or
unbuffered output compare/PWM operation.
See
When ELSxB:A = 00, this read/write bit selects the initial output level of the
TCHx pin (see
MSxB
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
1 = Initial output level low
0 = Initial output level high
Freescale Semiconductor, Inc.
X
X
0
0
0
0
0
0
0
1
1
1
Table
For More Information On This Product,
MSxA
15-3.
0
1
0
0
0
1
1
1
1
X
X
X
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Timer Interface Module (TIM)
Table
Table 15-3. Mode, Edge, and Level Selection
ELSxB
0
0
0
1
1
0
0
1
1
0
1
1
15-3). Reset clears the MSxA bit.
ELSxA
0
0
1
0
1
0
1
0
1
1
0
1
Output compare
buffered PWM
Output preset
Input capture
compare or
Buffered
or PWM
output
Mode
Pin under port control;
initial output level high
Pin under port control;
initial output level low
Capture on rising edge only
Capture on falling edge only
Capture on rising
or falling edge
Software compare only
Toggle output on compare
Clear output on compare
Set output on compare
Toggle output on compare
Clear output on compare
Set output on compare
Timer Interface Module (TIM)
Input/Output Registers
Configuration
Data Sheet
151