mc68hc908qf4 Freescale Semiconductor, Inc, mc68hc908qf4 Datasheet - Page 126

• Manufacturer Part Number: mc68hc908qf4
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

System Integration Module (SIM)
14.5 SIM Counter
14.5.1 SIM Counter During Power-On Reset
14.5.2 SIM Counter During Stop Mode Recovery
14.5.3 SIM Counter and Reset States
14.6 Exception Control
14.6.1 Interrupts
Data Sheet
126
The SIM counter is used by the power-on reset module (POR) and in stop mode
recovery to allow the oscillator time to stabilize before enabling the internal bus
(IBUS) clocks. The SIM counter also serves as a prescaler for the computer
operating properly module (COP). The SIM counter uses 12 stages for counting,
followed by a 13th stage that triggers a reset of SIM counters and supplies the clock
for the COP module. The SIM counter is clocked by the falling edge of BUSCLKX4.
The power-on reset module (POR) detects power applied to the MCU. At
power-on, the POR circuit asserts the signal PORRST. Once the SIM is initialized,
it enables the oscillator to drive the bus clock state machine.
The SIM counter also is used for stop mode recovery. The STOP instruction clears
the SIM counter. After an interrupt, break, or reset, the SIM senses the state of the
short stop recovery bit, SSREC, in the configuration register 1 (CONFIG1). If the
SSREC bit is a 1, then the stop recovery is reduced from the normal delay of 4096
BUSCLKX4 cycles down to 32 BUSCLKX4 cycles. This is ideal for applications
using canned oscillators that do not require long start-up times from stop mode.
External crystal applications should use the full stop recovery time, that is, with
SSREC cleared in the configuration register 1 (CONFIG1).
External reset has no effect on the SIM counter (see
The SIM counter is free-running after all reset states. See
from Internal Sources
Normal sequential program execution can be changed in three different ways:
An interrupt temporarily changes the sequence of program execution to respond to
a particular event.
1. Interrupts
2. Reset
3. Break interrupts
Freescale Semiconductor, Inc.
a. Maskable hardware CPU interrupts
b. Non-maskable software interrupt instruction (SWI)
For More Information On This Product,
System Integration Module (SIM)
Go to: www.freescale.com
Figure 14-8
for counter control and internal reset recovery sequences.
flow charts the handling of system interrupts.
14.7.2 Stop Mode
MC68HC908QF4 — Rev. 1.0
14.4.2 Active Resets
for details.)
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