mc68hc908qf4 Freescale Semiconductor, Inc, mc68hc908qf4 Datasheet - Page 143

• Manufacturer Part Number: mc68hc908qf4
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

15.4.4.1 Unbuffered PWM Signal Generation
MC68HC908QF4 — Rev. 1.0
MOTOROLA
NOTE:
Any output compare channel can generate unbuffered PWM pulses as described
in
changing the pulse width requires writing the new pulse width value over the old
value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change a pulse width
value could cause incorrect operation for up to two PWM periods. For example,
writing a new value before the counter reaches the old value but after the counter
reaches the new value prevents any compare during that PWM period. Also, using
a TIM overflow interrupt routine to write a new, smaller pulse width value may
cause the compare to be missed. The TIM may pass the new value before it is
written.
Use the following methods to synchronize unbuffered changes in the PWM pulse
width on channel x:
In PWM signal generation, do not program the PWM channel to toggle on output
compare. Toggling on output compare prevents reliable 0% duty cycle generation
and removes the ability of the channel to self-correct in the event of software error
or noise. Toggling on output compare also can cause incorrect PWM signal
generation when changing the PWM pulse width to a new, much larger value.
POLARITY = 1
POLARITY = 0
(ELSxA = 0)
(ELSxA = 1)
15.4.4 Pulse Width Modulation
•
•
When changing to a shorter pulse width, enable channel x output compare
interrupts and write the new value in the output compare interrupt routine.
The output compare interrupt occurs at the end of the current pulse. The
interrupt routine has until the end of the PWM period to write the new value.
When changing to a longer pulse width, enable TIM overflow interrupts and
write the new value in the TIM overflow interrupt routine. The TIM overflow
interrupt occurs at the end of the current PWM period. Writing a larger value
in an output compare interrupt routine (at the end of the current pulse) could
cause two output compares to occur in the same PWM period.
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Timer Interface Module (TIM)
Figure 15-4. PWM Period and Pulse Width
PULSE
WIDTH
PERIOD
COMPARE
OUTPUT
(PWM). The pulses are unbuffered because
OVERFLOW
COMPARE
OUTPUT
Timer Interface Module (TIM)
OVERFLOW
Functional Description
Data Sheet
COMPARE
OUTPUT
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