mc68hc908qf4 Freescale Semiconductor, Inc, mc68hc908qf4 Datasheet - Page 62

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mc68hc908qf4

Manufacturer Part Number
mc68hc908qf4
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Central Processor Unit (CPU)
7.3.4 Program Counter
7.3.5 Condition Code Register
Data Sheet
62
The program counter is a 16-bit register that contains the address of the next
instruction or operand to be fetched.
Normally, the program counter automatically increments to the next sequential
memory location every time an instruction or operand is fetched. Jump, branch,
and interrupt operations load the program counter with an address other than that
of the next sequential location.
During reset, the program counter is loaded with the reset vector address located
at $FFFE and $FFFF. The vector address is the address of the first instruction to
be executed after exiting the reset state.
The 8-bit condition code register contains the interrupt mask and five flags that
indicate the results of the instruction just executed. Bits 6 and 5 are set
permanently to 1. The following paragraphs describe the functions of the condition
code register.
V — Overflow Flag
Reset:
Reset:
Read:
Read:
Write:
Write:
The CPU sets the overflow flag when a two's complement overflow occurs. The
signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag.
1 = Overflow
0 = No overflow
Freescale Semiconductor, Inc.
X = Indeterminate
Bit
15
For More Information On This Product,
Bit 7
V
X
14
Figure 7-6. Condition Code Register (CCR)
13
Go to: www.freescale.com
Central Processor Unit (CPU)
6
1
1
Figure 7-5. Program Counter (PC)
12
11
Loaded with vector from $FFFE and $FFFF
5
1
1
10
9
H
X
4
8
7
3
1
I
6
5
N
X
2
4
MC68HC908QF4 — Rev. 1.0
3
Z
X
1
2
1
MOTOROLA
Bit 0
C
X
Bit
0

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