mc68hc908qf4 Freescale Semiconductor, Inc, mc68hc908qf4 Datasheet - Page 132

• Manufacturer Part Number: mc68hc908qf4
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

System Integration Module (SIM)
14.6.5 Status Flag Protection in Break Mode
14.7 Low-Power Modes
14.7.1 Wait Mode
Data Sheet
132
location. Refer to the break interrupt subsection of each module to see how each
module is affected by the break state.
The SIM controls whether status flags contained in other modules can be cleared
during break mode. The user can select whether flags are protected from being
cleared by properly initializing the break clear flag enable bit (BCFE) in the break
flag control register (BFCR).
Protecting flags in break mode ensures that set flags will not be cleared while in
break mode. This protection allows registers to be freely read and written during
break mode without losing status flag information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in break
mode, a flag remains cleared even when break mode is exited. Status flags with a
two-step clearing mechanism — for example, a read of one register followed by the
read or write of another — are protected, even when the first step is accomplished
prior to entering break mode. Upon leaving break mode, execution of the second
step will clear the flag as normal.
Executing the WAIT or STOP instruction puts the MCU in a low
power-consumption mode for standby situations. The SIM holds the CPU in a
non-clocked state. The operation of each of these modes is described below. Both
STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing
interrupts to occur.
In wait mode, the CPU clocks are inactive while the peripheral clocks continue to
run.
ADDRESS BUS
NOTE: Previous data can be operand data or the WAIT opcode, depending on the
Figure 14-15
DATA BUS
Freescale Semiconductor, Inc.
For More Information On This Product,
last instruction.
R/W
System Integration Module (SIM)
WAIT ADDR
Go to: www.freescale.com
shows the timing for wait mode entry.
Figure 14-15. Wait Mode Entry Timing
PREVIOUS DATA
WAIT ADDR + 1
NEXT OPCODE
SAME
MC68HC908QF4 — Rev. 1.0
SAME
SAME
SAME
MOTOROLA