mc68hc908qf4 Freescale Semiconductor, Inc, mc68hc908qf4 Datasheet - Page 41

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mc68hc908qf4

Manufacturer Part Number
mc68hc908qf4
Description
M68hc08 Microcontrollers Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
3.4 Interrupts
3.5 Low-Power Modes
3.5.1 Wait Mode
3.5.2 Stop Mode
3.6 Input/Output Signals
3.7 Input/Output Registers
MC68HC908QF4 — Rev. 1.0
MOTOROLA
When the AIEN bit is set, the ADC module is capable of generating a central
processor unit (CPU) interrupt after each ADC conversion. A CPU interrupt is
generated if the COCO bit is at 0. The COCO bit is not used as a conversion
complete flag when interrupts are enabled.
The following subsections describe the ADC in low-power modes.
The ADC continues normal operation during wait mode. Any enabled CPU interrupt
request from the ADC can bring the microcontroller unit (MCU) out of wait mode. If
the ADC is not required to bring the MCU out of wait mode, power down the ADC
by setting the CH[4:0] bits in ADSCR to 1s before executing the WAIT instruction.
The ADC module is inactive after the execution of a STOP instruction. Any pending
conversion is aborted. ADC conversions resume when the MCU exits stop mode.
Allow one conversion cycle to stabilize the analog circuitry before using ADC data
after exiting stop mode.
The ADC module has four channels that are shared with I/O port A.
ADC voltage in (ADCVIN) is the input voltage signal from one of the four ADC
channels to the ADC module.
These I/O registers control and monitor ADC operation:
ADC status and control register (ADSCR)
ADC data register (ADR)
ADC clock register (ADICLK)
Freescale Semiconductor, Inc.
For More Information On This Product,
Analog-to-Digital Converter (ADC)
Go to: www.freescale.com
Analog-to-Digital Converter (ADC)
Data Sheet
Interrupts
41

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