at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 1031

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

49.2.9
49.2.9.1
49.2.9.2
49.2.9.3
49.2.9.4
49.2.9.5
6249D–ATARM–20-Dec-07
MCI
Busy signal of R1b responses is not taken in account
SDIO interrupt does not work for slot different from A
Data Timeout Error Flag
Data Write Operation and Number of Bytes
Flag Reset is not correct in half duplex mode
1) BRSTLN = 3 implies the following LCD DMA Base Address offsets : 0x0, 0x30, 0x60, ...
2) BRSTLN = 15 implies the following LCD DMA Base Address offsets : 0x0 and 0xc0 only
The busy status of the card during the response (R1b) is ignored for the commands CMD7,
CMD28, CMD29, CMD38, CMD42, CMD56.
Additionally, for commands CMD42 and CMD56, a conflict can occur on data line 0 if the MCI
sends data to the card while the card is still busy.
The behavior is correct for CMD12 command (STOP_TRANSFER).
Problem Fix/Workaround
None
If data bus width is 1 bit and is on other slots than Slot A, the SDIO interrupt cannot be captured.
The sample is made on the bad data line.
Problem Fix/Workaround
None
As the data Timeout error flag checking the Naac timing cannot rise, the MCI can be stalled wait-
ing indefinitely the Data start bit.
Problem Fix/Workaround
A STOP command must be sent with a software timeout.
The Data Write operation with a number of bytes less than 12 is impossible.
Problem Fix/Workaround
The PDC counters must always be equal to 12 bytes for data transfers lower than 12 bytes. The
BLKLEN or BCNT field are used to specify the real count number.
In half duplex mode, the reset of the flags ENDRX, RXBUFF, ENDTX and TXBUFE can be
incorrect.
These flags are reset correctly after a PDC channel enable.
Problem Fix/Workaround
Enable the interrupts related to ENDRX, ENDTX, RXBUFF and TXBUFE only after enabling the
PDC channel by writing PDC_TXTEN or PDC_RXTEN.
AT91SAM9263 Preliminary
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