at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 307

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

24.4.4
Name: DMAC_CTLxL
Access: Read/Write
Reset: 0x0
The address offset for each channel is: 0x18+[x * 0x58]
For example, CTL0: 0x018, CTL1: 0x070, etc.
This register contains fields that control the DMA transfer. The DMAC_CTLxL register is part of the block descriptor (linked
list item) when block chaining is enabled. It can be varied on a block-by-block basis within a DMA transfer when block
chaining is enabled.
• INT_EN: Interrupt Enable Bit
If set, then all five interrupt generating sources are enabled.
• DST_TR_WIDTH: Destination Transfer Width
• SRC_TR_WIDTH: Source Transfer Width
• DINC: Destination Address Increment
Indicates whether to increment or decrement the destination address on every destination AMBA transfer. If your device is
writing data to a destination peripheral FIFO with a fixed address, then set this field to “No change”.
00 = Increment
01 = Decrement
1x = No change
• SINC: Source Address Increment
Indicates whether to increment or decrement the source address on every source AMBA transfer. If your device is fetching
data from a source peripheral FIFO with a fixed address, then set this field to “No change”.
00 = Increment
01 = Decrement
6249D–ATARM–20-Dec-07
SRC_TR_WIDTH/DST_TR_WIDTH
000
001
010
Other
DINC
DMS
31
23
15
–
7
SRC_MSIZE
Control Register for Channel x Low
30
22
14
–
6
SRC_TR_WIDTH
TT_FC
29
21
13
–
5
Size (bits)
8
16
32
Reserved
DEST_MSIZE
LLP_S_EN
28
20
12
4
LLP_D_EN
27
19
11
3
-
AT91SAM9263 Preliminary
DST_TR_WIDTH
D_SCAT_EN
26
18
10
2
SINC
SMS
S_GATH_EN
25
17
9
1
SRC_MSIZE
INT_EN
DINC
DMS
24
16
8
0
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