at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 41

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at91sam9263

Manufacturer Part Number
at91sam9263
Description
At91 Arm Thumb Microcontrollers
Manufacturer
ATMEL Corporation
Datasheet

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10.4.9
10.4.10
10.4.11
10.5
10.5.1
10.5.2
10.5.3
6249D–ATARM–20-Dec-07
Embedded Peripherals Overview
Interrupts
Image Sensor Interface
Timers
Serial Peripheral Interface
Two-wire Interface
USART
Using IRQ0 prevents using the CAN controller.
Using FIQ prevents using DMA Request 2.
Using ISI in 8-bit data mode prevents using timers TIOA1, TIOB1.
Using TIOA2 and TIOB2, in this order, prevents using SPI1’s Chip Selects [2-3].
• Supports communication with serial external devices
• Master or slave serial peripheral bus interface
• Very fast transfers supported
• Master Mode only
• Compatibility with standard two-wire serial memory
• One, two or three bytes for slave address
• Sequential read/write operations
• Programmable Baud Rate Generator
• 5- to 9-bit full-duplex synchronous or asynchronous serial communications
– Four chip selects with external decoder support allow communication with up to 15
– Serial memories, such as DataFlash and 3-wire EEPROMs
– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and
– External co-processors
– 8- to 16-bit programmable data length per chip select
– Programmable phase and polarity per chip select
– Programmable transfer delays between consecutive transfers and between clock
– Programmable delay between consecutive transfers
– Selectable mode fault detection
– Transfers with baud rates up to MCK
– The chip select line may be left active to speed up transfers on the same device
– 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode
– Parity generation and error detection
– Framing error detection, overrun error detection
– MSB- or LSB-first
peripherals
Sensors
and data per chip select
AT91SAM9263 Preliminary
41

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