at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 317

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at91sam9263

Manufacturer Part Number
at91sam9263
Description
At91 Arm Thumb Microcontrollers
Manufacturer
ATMEL Corporation
Datasheet

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24.4.11
Name: DMAC_RawTfr, DMAC_RawBlock, DMAC_RawSrcTran, DMAC_RawDstTran, DMAC_RawErr
Access: Read
Reset: 0x0
The address offset are
DMAC_RawTfr – 0x2c0
DMAC_RawBlock – 0x2c8
DMAC_RawSrcTran – 0x2d0
DMAC_RawDstTran – 0x2d8
DMAC_RawErr – 0x2e0
• RAW[1:0]: Raw interrupt for each channel
Interrupt events are stored in these Raw Interrupt Status Registers before masking: DMAC_RawTfr, DMAC_RawBlock,
DMAC_RawSrcTran, DMAC_RawDstTran, DMAC_RawErr. Each Raw Interrupt Status register has a bit allocated per
channel, for example, DMAC_RawTfr[2] is Channel 2’s raw transfer complete interrupt. Each bit in these registers is
cleared by writing a 1 to the corresponding location in the DMAC_ClearTfr, DMAC_ClearBlock, DMAC_ClearSrcTran,
DMAC_ClearDstTran, DMAC_ClearErr registers.
6249D–ATARM–20-Dec-07
31
23
15
7
Interrupt Raw Status Registers
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
AT91SAM9263 Preliminary
26
18
10
2
RAW1
25
17
9
1
RAW0
24
16
8
0
317

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