at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 488

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

32.5.5.1
Figure 32-10. Master Write with One, Two or Three Bytes Internal Address and One Data Byte
Figure 32-11. Master Read with One, Two or Three Bytes Internal Address and One Data Byte
488
TWD
TWD
TWD
TWD
TWD
TWD
Three bytes internal address
Two bytes internal address
One byte internal address
Three bytes internal address
Two bytes internal address
One byte internal address
S
S
S
AT91SAM9263 Preliminary
S
S
S
7-bit Slave Addressing
DADR
DADR
DADR
DADR
DADR
DADR
W
W
W
When Addressing 7-bit slave devices, the internal address bytes are used to perform random
address (read or write) accesses to reach one or more data bytes, within a memory page loca-
tion in a serial memory, for example. When performing read operations with an internal address,
the TWI performs a write operation to set the internal address into the slave device, and then
switch to Master Receiver mode. Note that the second start condition (after sending the IADR) is
sometimes called “repeated start” (Sr) in I2C fully-compatible devices. See
32-11
The three internal address bytes are configurable through the Master Mode register
(TWI_MMR).
If the slave device supports only a 7-bit address, i.e. no internal address, IADRSZ must be set to
0.
In the figures below the following abbreviations are used:
Table 32-3.
W
W
W
• S
• P
• W
• R
• A
• N
• DADR
• IADR
A
A
A
and
A
A
A
IADR(23:16)
IADR(15:8)
IADR(7:0)
Figure
IADR(23:16)
Start
Stop
Write
Read
Acknowledge
Not Acknowledge
Device Address
Internal Address
IADR(15:8)
IADR(7:0)
32-12.
A
A
A
IADR(15:8)
A
A
A
IADR(7:0)
S
DADR
IADR(15:8)
IADR(7:0)
DATA
A
A
R
IADR(7:0)
S
A
A
A
A
DADR
IADR(7:0)
P
DATA
DATA
A
S
R
A
A
A
N
DADR
DATA
P
DATA
P
DATA
Figure
6249D–ATARM–20-Dec-07
R
N
32-10,
A
P
A
N
P
P
Figure