at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 277

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

Figure 24-4. External DMA Request Timing
24.3.4
24.3.4.1
24.3.4.2
6249D–ATARM–20-Dec-07
nDMAREQx
dma_ack
dma_req
DMAC Transfer Types
Hclk
Multi-block Transfers
Block Chaining Using Linked Lists
For a source FIFO, an active edge is triggered on nDMAREQx when the source FIFO exceeds a
watermark level. For a destination FIFO, an active edge is triggered on nDMAREQx when the
destination FIFO drops below the watermark level.
The source transaction length, CTLx.SRC_MSIZE, and destination transaction length,
CTLx.DEST_MSIZE, must be set according to watermark levels on the source/destination
peripherals.
A DMA transfer may consist of single or multi-block transfers. On successive blocks of a multi-
block transfer, the DMAC_SARx/DMAC_DARx register in the DMAC is reprogrammed using
either of the following methods:
On successive blocks of a multi-block transfer, the DMAC_CTLx register in the DMAC is re-pro-
grammed using either of the following methods:
When block chaining, using linked lists is the multi-block method of choice, and on successive
blocks, the DMAC_LLPx register in the DMAC is re-programmed using the following method:
A block descriptor (LLI) consists of following registers, DMAC_SARx, DMAC_DARx,
DMAC_LLPx, DMAC_CTLx. These registers, along with the DMAC_CFGx register, are used by
the DMAC to set up and describe the block transfer.
In this case, the DMAC re-programs the channel registers prior to the start of each block by
fetching the block descriptor for that block from system memory. This is known as an LLI update.
• Block chaining using linked lists
• Auto-reloading
• Contiguous address between blocks
• Block chaining using linked lists
• Auto-reloading
• Block chaining using linked lists
DMA Transfers
DMA Transaction
DMA Transfers
AT91SAM9263 Preliminary
DMA Transfers
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