at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 295

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

Figure 24-13. Multi-block Transfer with Source Address Auto-reloaded and Contiguous Destination Address
6249D–ATARM–20-Dec-07
Address of
Source Layer
The transfer is similar to that shown in
The DMA Transfer flow is shown in
a. If interrupts are enabled (DMAC_CTLx.INT_EN = 1) and the block complete inter-
b. If interrupts are disabled (DMAC_CTLx.INT_EN = 0) or the block complete interrupt
SAR
rupt is un-masked (DMAC_MaskBlock[x] = 1’b1, where x is the channel number)
hardware sets the block complete interrupt when the block transfer has completed.
It then stalls until the block complete interrupt is cleared by software. If the next
block is to be the last block in the DMA transfer, then the block complete ISR (inter-
rupt service routine) should clear the source reload bit,
DMAC_CFGx.RELOAD_SR. This puts the DMAC into Row1 as shown in
2 on page
source reload bit should remain enabled to keep the DMAC in Row3 as shown in
Table 24-2 on page
is masked (DMAC_MaskBlock[x] = 1’b0, where x is the channel number) then hard-
ware does not stall until it detects a write to the block complete interrupt clear
register but starts the next block transfer immediately. In this case software must
clear the source reload bit, DMAC_CFGx.RELOAD_SR, to put the device into
ROW 1 of
completed.
Source Blocks
Table 24-2 on page 278
278. If the next block is not the last block in the DMA transfer then the
278.
Figure 24-14 on page
Block2
Block0
Block1
Figure 24-13 on page
Destination Blocks
AT91SAM9263 Preliminary
before the last block of the DMA transfer has
DAR(2)
DAR(1)
DAR(0)
Destination Layer
296.
Address of
295.
Table 24-
295