at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 873

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

6249D–ATARM–20-Dec-07
Table 43-8.
The duty cycles for gray levels 0 and 15 are 0 and 1, respectively.
The same DP_i register can be used for the pairs for which the sum of duty cycles is 1 (e.g., 1/7
and 6/7). The dithering pattern for the first pair member is the inversion of the one for the
second.
The DP_i registers contain a series of 4-bit patterns. The (3-m)
pixel with horizontal coordinate x = 4n + m (n is an integer and m ranges from 0 to 3) should be
turned on or off in the current frame. The operation is shown by the examples below.
Consider the pixels a, b, c and d with the horizontal coordinates 4*n+0, 4*n+1, 4*n+2 and 4*n+3,
respectively. The four pixels should be displayed in gray level 9 (duty cycle 3/5) so the register
used is DP3_5 =”1010 0101 1010 0101 1111”.
The output sequence obtained in the data output for monochrome mode is shown in
Table 43-9.
Consider now color display mode and two pixels p0 and p1 with the horizontal coordinates
4*n+0, and 4*n+1. A color pixel is composed of three components: {R, G, B}. Pixel p0 will be dis-
played sending the color components {R0, G0, B0} to the display. Pixel p1 will be displayed
sending the color components {R1, G1, B1}. Suppose that the data read from memory and
Gray Level
9
8
7
6
5
4
3
2
1
0
Frame
Number
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
...
Dithering Duty Cycle
Dithering Algorithm for Monochrome Mode
Pattern
1010
0101
1010
0101
1111
1010
0101
1010
...
ON
OFF
ON
OFF
ON
ON
OFF
ON
...
Duty Cycle
3/5
4/7
1/2
3/7
2/5
1/3
1/4
1/5
1/7
0
Pixel a
AT91SAM9263 Preliminary
Pixel b
OFF
ON
OFF
ON
ON
OFF
ON
OFF
...
Pixel c
ON
OFF
ON
OFF
ON
ON
OFF
ON
...
Pattern Register
DP3_5
DP4_7
~DP1_2
~DP4_7
~DP3_5
~DP2_3
~DP3_4
~DP4_5
~DP6_7
-
th
bit of the pattern determines if a
Pixel d
OFF
ON
OFF
ON
ON
OFF
ON
OFF
...
Table
43-9.
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