at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 1038

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

49.2.19
49.2.19.1
49.2.19.2
49.2.19.3
49.2.19.4
49.2.19.5
1038
AT91SAM9263 Preliminary
USART
SCK1 and SCK2 are Inverted
RXBRK Flag Error in Asynchronous Mode
RTS not Expected Behavior
Two characters sent if CTS rises during emission
TXD signal is floating in Modem and Hardware Handshaking mod
Consequence: If the Device does not recognize the resume (<20 ms) event then the Device, it
will remain in the suspend state.
Problem Fix/Workaround
Host stack can do a port resume after it sets the HcControl.HCFS to USBOPERATIONAL.
SCK1 and SCK2 clocks are inverted on the PIO controller, but the enable of the clocks is
correct.
This makes it impossible to use USART1 and USART2 in Synchronous Mode.
Problem Fix/ Workaround
To use USART1 in Synchronous Mode, the user must program USART1 and USART2 with
exactly the same configuration. SCK2 clock will output on PD10.
Note : EBI0_CFCE2 usage on "periph A" is not forbidden because PD9 is SCK1 which is not
used.
When timeguard is 0, RXBRK is not set when the break character is located just after the Stop
Bit. FRAME (Frame Error) is set instead.
Problem Fix/Workaround
Timeguard should be > 0.
Problem Fix/Workaround
None.
If CTS rises to 1 during a character transmit, the Transmit Holding Register is also transmitted if
not empty.
Problem Fix/Workaround
None.
TXD signal should be pulled up in Modem and Hardware Handshaking mode.
Problem Fix/Workaround
TXD is multiplexed with PIO which integrates a pull up resistor. This internal pull-up must be
enabled.
1. Setting the receiver to hardware handshaking mode drops RTS line to low level even if
2. Disabling the receiver during a PDC transfer while RXBUFF flag is '0' has no effect on
the receiver is still turned off. USART needs to be completely configured and started
before setting the receiver to hardware handshaking mode.
RTS. The only way to get the RTS line to rise to high level is to reset both PDMA buffers
by writing the value '0' in both counter registers.
6249D–ATARM–20-Dec-07