at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 319

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

24.4.13
Name: DMAC_MaskTfr, DMAC_MaskBlock, DMAC_MaskSrcTran, DMAC_MaskDstTran, DMAC_MaskErr
Access: Read/Write
Reset: 0x0
The address offset are
DMAC_MaskTfr: 0x310
DMAC_MaskBlock: 0x318
DMAC_MaskSrcTran: 0x320
DMAC_MaskDstTran: 0x328
DMAC_MaskErr: 0x330
The contents of the Raw Status Registers are masked with the contents of the Mask Registers: DMAC_MaskTfr,
DMAC_MaskBlock, DMAC_MaskSrcTran, DMAC_MaskDstTran, DMAC_MaskErr. Each Interrupt Mask register has a bit
allocated per channel, for example, DMAC_MaskTfr[2] is the mask bit for Channel 2’s transfer complete interrupt.
A channel’s INT_MASK bit is only written if the corresponding mask write enable bit in the INT_MASK_WE field is asserted
on the same AMBA write transfer. This allows software to set a mask bit without performing a read-modified write
operation.
For example, writing hex 01x1 to the DMAC_MaskTfr register writes a 1 into DMAC_MaskTfr[0], while DMAC_MaskTfr[7:1]
remains unchanged. Writing hex 00xx leaves DMAC_MaskTfr[7:0] unchanged.
Writing a 1 to any bit in these registers unmasks the corresponding interrupt, thus allowing the DMAC to set the appropriate
bit in the Status Registers.
• INT_MASK[1:0]: Interrupt Mask
0 = Masked
1 = Unmasked
• INT_M_WE[9:8]: Interrupt Mask Write Enable
0 = Write disabled
1 = Write enabled
6249D–ATARM–20-Dec-07
31
23
15
–
–
–
7
–
Interrupt Status Registers
30
22
14
–
–
–
6
–
29
21
13
–
–
–
5
–
28
20
12
–
–
–
4
–
27
19
11
–
–
–
3
–
AT91SAM9263 Preliminary
26
18
10
–
–
–
2
–
INT_M_WE1
INT_MASK1
25
17
–
–
9
1
INT_M_WE0
INT_MASK0
24
16
–
–
8
0
319