at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 311

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

24.4.6
Name: DMAC_CFGxL
Access: Read/Write
Reset: 0x0
The address offset for each channel is: 0x40+[x * 0x58]
For example, CFG0: 0x040, CFG1: 0x098, etc.
• CH_PRIOR: Channel priority
A priority of 7 is the highest priority, and 0 is the lowest. This field must be programmed within the following range [0, x – 1]
A programmed value outside this range causes erroneous behavior.
• CH_SUSP: Channel Suspend
Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction
will complete. Can also be used in conjunction with DMAC_CFGx.FIFO_EMPTY to cleanly disable a channel without losing
any data.
0 = Not Suspended.
1 = Suspend. Suspend DMA transfer from the source.
• FIFO_EMPTY
Indicates if there is data left in the channel's FIFO. Can be used in conjunction with DMAC_CFGx.CH_SUSP to cleanly dis-
able a channel.
1 = Channel's FIFO empty
0 = Channel's FIFO not empty
• HS_SEL_DST: Destination Software or Hardware Handshaking Select
This register selects which of the handshaking interfaces, hardware or software, is active for destination requests on this
channel.
0 = Hardware handshaking interface. Software-initiated transaction requests are ignored.
1 = Software handshaking interface. Hardware Initiated transaction requests are ignored.
If the destination peripheral is memory, then this bit is ignored.
• HS_SEL_SRC: Source Software or Hardware Handshaking Select
This register selects which of the handshaking interfaces, hardware or software, is active for source requests on this
channel.
0 = Hardware handshaking interface. Software-initiated transaction requests are ignored.
6249D–ATARM–20-Dec-07
RELOAD_DS
31
23
15
7
LOCK_B_L
Configuration Register for Channel x Low
RELOAD_SR
CH_PRIOR
30
22
14
6
MAX_ABRST
29
21
13
5
LOCK_CH_L
28
20
12
4
–
SR_HS_POL
HS_SEL_SR
27
19
11
3
–
MAX_ABRST
AT91SAM9263 Preliminary
DS_HS_POL
HS_SEL_DS
26
18
10
2
–
FIFO_EMPT
LOCK_B
25
17
9
1
–
LOCK_CH
CH_SUSP
24
16
8
0
–
311