at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 15

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

7.2
6249D–ATARM–20-Dec-07
Bus Matrix
• 16 Kbyte Data Cache, 16 Kbyte Instruction Cache
• Write Buffer
• Standard ARM v4 and v5 Memory Management Unit (MMU)
• Bus Interface Unit (BIU)
• 9-layer Matrix, handling requests from 9 masters
• Programmable Arbitration strategy
• Burst Management
• One Address Decoder provided per Master
• Boot Mode Select
– Instruction Fetch (F)
– Instruction Decode (D)
– Execute (E)
– Data Memory (M)
– Register Write (W)
– Virtually-addressed 4-way Associative Cache
– Eight words per line
– Write-through and Write-back Operation
– Pseudo-random or Round-robin Replacement
– Main Write Buffer with 16-word Data Buffer and 4-address Buffer
– DCache Write-back Buffer with 8-word Entries and a Single Address Entry
– Software Control Drain
– Access Permission for Sections
– Access Permission for large pages and small pages can be specified separately for
– 16 embedded domains
– Arbitrates and Schedules AHB Requests
– Separate Masters for both instruction and data access providing complete Matrix
– Separate Address and Data Buses for both the 32-bit instruction interface and the
– On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit
– Fixed-priority Arbitration
– Round-Robin Arbitration, either with no default master, last accessed default master
– Breaking with Slot Cycle Limit Support
– Undefined Burst Length Support
– Three different slaves may be assigned to each decoded memory area: one for
– Non-volatile Boot Memory can be internal or external
each quarter of the page
system flexibility
32-bit data interface
(Words)
or fixed default master
internal boot, one for external boot, one after remap
AT91SAM9263 Preliminary
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