at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 1035

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

49.2.14
49.2.14.1
49.2.14.2
49.2.14.3
49.2.14.4
49.2.15
49.2.15.1
6249D–ATARM–20-Dec-07
Serial Synchronous Controller (SSC)
System Controller
Transmitter Limitations in Slave Mode
Periodic Transmission Limitations in Master Mode
SSC: Last RK Clock Cycle when RK Outputs a Clock During Data Transfer
SSC: First RK Clock Cycle when Rk Outputs a Clock During Data Transfer
Possible Event Loss when Reading RTT_SR
If TK is programmed as output and TF is programmed as input, it is impossible to emit data
when start of edge (rising or falling) of synchro with a Start Delay equal to zero.
Problem Fix/Workaround
None.
If Last Significant Bit is sent first (MSBF = 0), the first TAG during the frame synchro is not sent.
Problem Fix/Workaround
None.
When the SSC receiver is used with the following conditions:
At the end of the data, the RK pin is set in high impedance which might be seen as an unex-
pected clock cycle.
Enable the pull-up on RK pin.
When the SSC receiver is used with the following conditions:
The first clock cycle time generated by the RK pin is equal to MCK/(2 x (value +1)).
None.
If an event (RTTINC or ALMS) occurs within the same slow clock cycle as when RTT_SR is
read, the corresponding bit may be cleared. This may lead to the loss of this event.
Problem Fix/Workaround
The software must handle the RTT event as an interrupt and should not poll RTT_SR.
• the internal clock divider is used (CKS = 0 and DIV different from 0)
• RK pin set as output and provides the clock during data transfer (CKO = 2)
• data sampled on RK falling edge (CKI = 0),
• RX clock is divided clock (CKS = 0 and DIV different from 0)
• RK pin set as output and provides the clock during data transfer (CKO = 2)
• data sampled on RK falling edge (CKI = 0),
Problem Fix/Workaround
Problem Fix/Workaround
AT91SAM9263 Preliminary
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