at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 865

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

43.3
Table 43-1.
43.4
43.4.1
43.4.2
43.4.3
43.5
43.5.1
43.5.1.1
43.5.1.2
6249D–ATARM–20-Dec-07
Name
LCDCC
LCDHSYNC
LCDDOTCK
LCDVSYNC
LCDDEN
LCDD[23:0]
I/O Lines Description
Product Dependencies
Functional Description
I/O Lines
Power Management
The LCD Controller is not continuously clocked. The user must first enable the LCD Controller clock in the
Power Management Controller before using it (PMC_PCER). Interrupt Sources
DMA Controller
Configuration Block
AHB Interface
I/O Lines Description
Description
Contrast control signal
Line synchronous signal (STN) or Horizontal synchronous signal (TFT)
LCD clock signal (STN/TFT)
Frame synchronous signal (STN) or Vertical synchronization signal (TFT)
Data enable signal
LCD Data Bus output
The pins used for interfacing the LCD Controller may be multiplexed with PIO lines. The pro-
grammer must first program the PIO Controller to assign the pins to their peripheral function. If
I/O lines of the LCD Controller are not used by the application, they can be used for other pur-
poses by the PIO Controller.
The LCD Controller interrupt line is connected to one of the internal sources of the Advanced
Interrupt Controller. Using the LCD Controller interrupt requires prior programming of the AIC.
The LCD Controller consists of two main blocks
and the LCD controller core (LCDC core). The DMA controller reads the display data from an
external memory through a AHB master interface. The LCD controller core formats the display
data. The LCD controller core continuously pumps the pixel data into the LCD module via the
LCD data bus (LCDD[23:0]); this bus is timed by the LCDDOTCK, LCDDEN, LCDHSYNC, and
LCDVSYNC signals.
The configuration block is a set of programmable registers that are used to configure the DMA
controller operation. These registers are written via the AHB slave interface. Only word access is
allowed.
For details on the configuration registers, see
891.
This block generates the AHB transactions. It generates undefined-length incrementing bursts
as well as 4- ,8- or 16-beat incrementing bursts. The size of the transfer can be configured in the
AT91SAM9263 Preliminary
“LCD Controller (LCDC) User Interface” on page
(Figure 43-1 on page
864), the DMA controller
Output
Output
Output
Type
Output
Output
Output
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