at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 353

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

Figure 27-1. Master Clock Controller
27.3
27.4
Figure 27-2. USB Clock Controller
27.5
6249D–ATARM–20-Dec-07
Processor Clock Controller
USB Clock Controller
Peripheral Clock Controller
MAINCK
PLLACK
PLLBCK
SLCK
The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle
Mode. The Processor Clock can be disabled by writing the System Clock Disable Register
(PMC_SCDR). The status of this clock (at least for debug purpose) can be read in the System
Clock Status Register (PMC_SCSR).
The Processor Clock PCK is enabled after a reset and is automatically re-enabled by any
enabled interrupt. The Processor Idle Mode is achieved by disabling the Processor Clock, which
is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the
product.
When the Processor Clock is disabled, the current instruction is finished before the clock is
stopped, but this does not prevent data transfers from other masters of the system bus.
The USB Source Clock is always generated from the PLL B output. If using the USB, the user
must program the PLL to generate a 48 MHz, a 96 MHz or a 192 MHz signal with an accuracy of
± 0.25% depending on the USBDIV bit in CKGR_PLLBR (see
When the PLL B output is stable, i.e., the LOCKB is set:
The Power Management Controller controls the clocks of each embedded peripheral by the way
of the Peripheral Clock Controller. The user can individually enable and disable the Master
• The USB host clock can be enabled by setting the UHP bit in PMC_SCER. To save power on
Source
Clock
USB
this peripheral when it is not used, the user can set the UHP bit in PMC_SCDR. The UHP bit
in PMC_SCSR gives the activity of this clock. The USB host port require both the 12/48 MHz
signal and the Master Clock. The Master Clock may be controlled via the Master Clock
Controller.
PMC_MCKR
CSS
USBDIV
Divider
/1,/2,/4
Master Clock
PMC_MCKR
Prescaler
PRES
UDP
UHP
AT91SAM9263 Preliminary
PMC_MCKR
Master
Divider
Clock
MDIV
UDP Clock (UDPCK)
UHP Clock (UHPCK)
MCK
To the Processor
Clock Controller (PCK)
Figure
27-2).
353