cx82100 Conexant Systems, Inc., cx82100 Datasheet - Page 38

• Manufacturer Part Number: cx82100
• Description: Home Network Processor Hnp
• Manufacturer: Conexant Systems, Inc.

Table 2-3. CX82100 HNP Pin Signal Definitions
2-8
VDD
VDDA
VDDO
VDDO
VGG
VSS
VSSA
VSSO
VSSO
VSSO
HRST#
BOPT (GPIO14)
PLLBP
CLKI
BCLKIO/GPIO38
FCLKIO/GPIO39
Pin Signal
H7, H8
G6
A12, B3, B5,
D1, D14, F6,
F9, F12, H10,
J7, K7, K11,
N5, N9, N11,
P1
N13 (CX82100
-11/-12/-51/-52)
H6
G7, G8
H5
A5, B9, B11,
C4, D8, D12,
F4, G9, H11,
K13, L2, N8,
P2, P5, P9,
P11
N13 (CX82100
–41/-42)
P13 (CX82100
-11/-12/-51/-52)
N14
K4
J3
J2
J5
J1
Pin No.
Conexant Proprietary and Confidential Information
CX82100 Home Network Processor Data Sheet
P
P
P
P
R
G
G
G
G
G
I
I/O
I
I
I/O
I/O
I/O
PWR
PWR
PWR
PWR
REF
GND
GND
GND
GND
GND
Ith
Itpu/Ot4
Itpd
Ith
Itpu/Ot4
Itpu/Ot4
I/O Type
Power and Ground
System Control
Clock Interface
Core Supply Voltage. Connect to +1.8V.
Supply Voltage. Connect to +1.8V through filter.
I/O Supply Voltage. Connect to +3.3V.
I/O Supply Voltage. Connect to +3.3V.
I/O Clamp Power Supply. Connect to +5V if available, otherwise
connect to +3.3V.
Core Ground. Connect to digital ground.
Ground. Connect to digital ground.
I/O Ground. Connect to digital ground.
I/O Ground. Connect to digital ground.
I/O Ground. Connect to digital ground.
Reset. Active low input asserted for at least 100 µs to reset the
HNP. All hardware registers are initialized to their default state.
Upon de-assertion of HRST#, the HNP executes the Boot Loader
code (see BOPT pin) then starts processing of the application
code.
Connect HRST# to a reset circuit.
Boot Loader Option. Upon de-assertion of the HRST# signal, the
Boot Loader code executes from internal ROM (BOPT pin high, i.e.,
open) or Flash ROM (BOPT pin low, i.e., connected to GND).
For normal operation, typically connect BOPT to GND through
4.7 kΩ to execute Boot Loader from Flash ROM.
PLL Bypass Mode Select. If the PLLBP pin is high (test mode),
pins FCLKIO and BCLKIO are FCLKIO and BCLKIO inputs only
(i.e., not GPIO pins). If the PLLBP pin is low (normal operation),
pins FCLKIO and BCLKIO operate as FCLKIO/GPIO39 and
BCLKIO/GPIO38 as selected in the GPIO_OPT register).
For normal operation, connect PLLBP to GND through 4.7 kΩ.
Clock In. Connect to 35.328 MHz voltage controlled crystal
oscillator (VCXO) output through 51 Ω.
Bit Clock I/O. If PLLBP pin is high (test mode), this pin is BCLKIO
input only (i.e., not GPIO38). If the PLLBP pin is low (normal
operation), this pin can be used as GPIO38 or BCLKIO (see
GPIO_OPT register bit 6 and PLLBP pin).
For normal operation, BCLKIO output supplies the 25 MHz to the
LAN1 and LAN2 interfaces. Connect BCLKIO to the LAN 1 X1 pin
and to the LAN2 X1 pin though a single 51 Ω resistor.
Frame Clock I/O. If the PLLBP pin is high (test mode), this pin is
FCLKIO input only (i.e., not GPIO39). If the PLLBP pin is low
(normal operation), this pin can be used as GPIO39 or FCLKIO
(see GPIO_OPT register bit 7 and PLLBP pin).
Signal Name/Description
101306C