cx82100 Conexant Systems, Inc., cx82100 Datasheet - Page 51

• Manufacturer Part Number: cx82100
• Description: Home Network Processor Hnp
• Manufacturer: Conexant Systems, Inc.

2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
101306C
Interface Timing and Waveforms
External Memory Interface (SDRAM)
Host Interface Timing
EMAC Interface Timing
USB Interface Timing
GPIO Interface Timing
Conexant Proprietary and Confidential Information
The External Memory Interface provides a PC100-compatible SDRAM interface. Signal
interface timing is summarized in Figure 2-5.
Note that MCLK is derived from the BCLK PLL output (see Section 12). Accordingly,
there is no fixed relationship between the HNP clock input (CLKI pin) and the External
Memory Interface signals.
Figure 2-5. External Memory Interface Timing
The signal interface timing for the Host Interface is user programmable. By programming
the registers associated with the Host interface, desired timing characteristics such as
read/write pulse widths and setup and hold times can be established. For details regarding
Host Interface timing, refer to Section 5.1.5.
To be added.
To be added.
The GPIO outputs are derived from the BCLK PLL output (see clocking chapter).
Accordingly, there is no fixed relationship between the HNP’s clock input (CLKI) and
the GPIO signals.
MCKE, MA[11:0] MB[1:0], MM[1:0],
CX82100 Home Network Processor Data Sheet
MD[15:0] (from SDRAM)
MCAS#, MRAS#, MW E#
MD[15:0] (to SDRAM)
MCLK
7.5 ns m ax.
1 ns m in.
10 ns m in.
4 ns min.
1 ns m in.
101545_072
2-21