MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 119

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MC68HC08AZ60ACFU

Manufacturer Part Number
MC68HC08AZ60ACFU
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
MC68HC08AZ60A — Rev 0.0
MOTOROLA
SIM Reset Status Register (SRSR)
SIM Break Status Register (SBSR)
SIM Break Flag Control Register
PIN LOGIC
RESET
Register Name
SIM RESET STATUS REGISTER
(SBFCR)
RESET PIN CONTROL
AND PRIORITY DECODE
INTERRUPT CONTROL
POR CONTROL
STOP/WAIT
CONTROL
CONTROL
Table 8-1. SIM I/O Register Summary
CLOCK
Figure 8-1. SIM Block Diagram
W:
W:
R:
R: POR
System Integration Module (SIM)
BCFE
Bit 7
R
R
CLOCK GENERATORS
RESET
= Reserved for factory test
COUNTER
PIN
R
R
6
SIM
2
CONTROL
MASTER
RESET
COP
R
R
5
ILOP
R
R
4
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO CGM)
COP CLOCK
CGMXCLK (FROM CGM)
CGMOUT (FROM CGM)
INTERNAL CLOCKS
LVI (FROM LVI MODULE)
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP (FROM COP MODULE)
CPU INTERFACE
INTERRUPT SOURCES
ILAD
R
R
3
System Integration Module (SIM)
R
R
2
0
= Unimplemented
BW
LVI
Advance Information
R
1
0
Bit 0 Addr.
R
R
0
Introduction
$FE00
$FE01
$FE03
119

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