MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 143

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MC68HC08AZ60ACFU

Manufacturer Part Number
MC68HC08AZ60ACFU
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
9.4.2 Phase-Locked Loop Circuit (PLL)
9.4.2.1 Circuits
MC68HC08AZ60A — Rev 0.0
MOTOROLA
PLL Programming Register (PPG)
PLL Bandwidth Control Register
PLL Control Register (PCTL)
Register Name
(PBWC)
The PLL is a frequency generator that can operate in either acquisition
mode or tracking mode, depending on the accuracy of the output
frequency. The PLL can change between acquisition and tracking
modes either automatically or manually.
The PLL consists of these circuits:
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Table 9-1. I/O Register Address Summary
Register
Address
Figure 9-2. I/O Register Summary
Voltage-controlled oscillator (VCO)
Modulo VCO frequency divider
Phase detector
Loop filter
Lock detector
AUTO
Bit 7
PLLIE
MUL7
0
0
0
Clock Generator Module (CGM)
$001C
PCTL
= Unimplemented
LOCK
MUL6
PLLF
6
0
0
1
PLLON
MUL5
ACQ
5
1
0
1
PBWC
$001D
MUL4
BCS
XLD
4
0
0
0
$001E
PPG
VRS7
3
1
1
0
0
0
Clock Generator Module (CGM)
VRS6
2
1
1
0
0
1
Functional Description
Advance Information
VRS5
1
1
1
0
0
1
Bit 0
VRS4
1
1
0
0
0
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