MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 157

• Manufacturer Part Number: MC68HC08AZ60ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

9.6.3 PLL Programming Register
MC68HC08AZ60A — Rev 0.0
MOTOROLA
Address:
Bits 3–0 — Reserved for Test
The PLL programming register contains the programming information for
the modulo feedback divider and the programming information for the
hardware configuration of the VCO.
MUL7–MUL4 — Multiplier Select Bits
Reset:
Read:
Write:
1. Write a logic 1 to XLD.
2. Wait N
3. Read XLD.
To check the status of the crystal reference, do the following:
The crystal loss detect function works only when the BCS bit is set,
selecting CGMVCLK to drive CGMOUT. When BCS is clear, XLD
always reads as logic 0.
These bits enable test functions not available in user mode. To ensure
software portability from development systems to user applications,
software should write 0s to bits 3–0 when writing to PBWC.
These read/write bits control the modulo feedback divider that selects
the VCO frequency multiplier, N. (See
Programming the PLL
select bits configures the modulo feedback divider the same as a
value of $1. Reset initializes these bits to $6 to give a default multiply
value of 6.
$001E
MUL7
Bit 7
0
Figure 9-6. PLL Programming Register (PPG)
Clock Generator Module (CGM)
4 cycles. N is the VCO frequency multiplier.
MUL6
6
1
MUL5
5
1
on page 147). A value of $0 in the multiplier
MUL4
4
0
VRS7
Circuits
3
0
Clock Generator Module (CGM)
VRS6
on page 143 and
2
1
Advance Information
VRS5
CGM Registers
1
1
VRS4
Bit 0
0
157