MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 274

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MC68HC08AZ60ACFU

Manufacturer Part Number
MC68HC08AZ60ACFU
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
Serial Peripheral Interface (SPI)
17.13.1 SPI Control Register (SPCR)
Advance Information
274
SPCR
Reset:
Read:
Write:
The SPI control register does the following:
SPRIE — SPI Receiver Interrupt Enable
SPMSTR — SPI Master
SPRIE
This read/write bit enables CPU interrupt requests generated by the
SPRF bit. The SPRF bit is set when a byte transfers from the shift
register to the receive data register. Reset clears the SPRIE bit.
This read/write bit selects master mode operation or slave mode
operation. Reset sets the SPMSTR bit.
Bit 7
R
0
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
1 = Master mode
0 = Slave mode
Enables SPI module interrupt requests
Selects CPU interrupt requests
Configures the SPI module as master or slave
Selects serial clock polarity and phase
Configures the SPSCK, MOSI, and MISO pins as open-drain
outputs
Enables the SPI module
Figure 17-12. SPI Control Register (SPCR)
= Reserved
Serial Peripheral Interface (SPI)
R
6
0
SPMSTR
5
1
CPOL
4
0
CPHA
3
1
SPWOM
MC68HC08AZ60A — Rev 0.0
2
0
SPE
1
0
MOTOROLA
SPTIE
Bit 0
0

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