MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 327

• Manufacturer Part Number: MC68HC08AZ60ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

20.6.2 Data Direction Register D (DDRD)
MC68HC08AZ60A — Rev 0.0
MOTOROLA
NOTE:
DDRD
$0007
Reset:
Read:
Write:
TACLK/TBCLK — Timer clock input
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic one to a DDRD bit enables the output buffer
for the corresponding port D pin; a logic zero disables the output buffer.
DDRD[7:0] — Data Direction Register D Bits
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Figure 20-12
When bit DDRDx is a logic one, reading address $0003 reads the PTDx
data latch. When bit DDRDx is a logic zero, reading address $0003
reads the voltage level on the pin. The data latch can always be written,
The PTD6/ATD14/TACLK pin is the external clock input for the TIMA.
The PTD4/TBCLK pin is the external clock input for the TIMB.The
prescaler select bits, PS[2:0], select PTD6/ATD14/TACLK or
PTD4/TBCLK as the TIM clock input (see
Control Registers
Register
PTD6/TAClk and PTD4/TBCLK are available for general purpose I/O.
While TACLK/TBCLK are selected, corresponding DDRD bits have
no effect.
These read/write bits control port D data direction. Reset clears
DDRD[7:0], configuring all port D pins as inputs.
DDRD7
Figure 20-11. Data Direction Register D (DDRD)
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
Bit 7
0
on page 295). When not selected as the TIM clock,
DDRD6
shows the port D I/O logic.
6
0
I/O Ports
DDRD5
on page 424 and
5
0
DDRD4
4
0
DDRD3
TIMB Status and Control
3
0
TIMA Channel Status and
DDRD2
2
0
Advance Information
DDRD1
1
0
I/O Ports
DDRD0
Bit 0
Port D
0
327