MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 437

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MC68HC08AZ60ACFU

Manufacturer Part Number
MC68HC08AZ60ACFU
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
24.4.4 Continuous Conversion
24.4.5 Accuracy and Precision
24.5 Interrupts
24.6 Low-Power Modes
24.6.1 Wait Mode
MC68HC08AZ60A — Rev 0.0
MOTOROLA
In the continuous conversion mode, the ADC data register will be filled
with new data after each conversion. Data from the previous conversion
will be overwritten whether that data has been read or not. Conversions
will continue until the ADCO bit (ADC status control register, $0038) is
cleared. The COCO bit is set after the first conversion and will stay set
for the next several conversions until the next write of the ADC status
and control register or the next read of the ADC data register.
The conversion process is monotonic and has no missing codes. See
Electrical Specifications
When the AIEN bit is set, the ADC module is capable of generating a
CPU interrupt after each ADC conversion. A CPU interrupt is generated
if the COCO bit (ADC status control register, $0038) is at logic 0. If the
COCO bit is set, an interrupt is generated. The COCO bit is not used as
a conversion complete flag when interrupts are enabled.
The following subsections describe the low-power modes.
The ADC continues normal operation during wait mode. Any enabled
CPU interrupt request from the ADC can bring the MCU out of wait
mode. If the ADC is not required to bring the MCU out of wait mode,
power down the ADC by setting the ADCH[4:0] bits in the ADC status
and control register before executing the WAIT instruction.
Analog-to-Digital Converter (ADC-15)
on page 445 for accuracy information.
Analog-to-Digital Converter (ADC-15)
Advance Information
Interrupts
437

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