MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 309

• Manufacturer Part Number: MC68HC08AZ60ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

19.8 I/O Registers
19.8.1 PIT Status and Control Register
MC68HC08AZ60A — Rev 0.0
MOTOROLA
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.
The following I/O registers control and monitor operation of the PIT:
The PIT status and control register:
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PIT status and control register (PSC)
PIT counter registers (PCNTH–PCNTL)
PIT counter modulo registers (PMODH–PMODL)
Enables PIT interrupt
Flags PIT overflows
Stops the PIT counter
Resets the PIT counter
Prescales the PIT counter clock
Programmable Interrupt Timer (PIT)
Programmable Interrupt Timer (PIT)
Advance Information
I/O Registers
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