MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 125

• Manufacturer Part Number: MC68HC08AZ60ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

8.4.2.2 Computer Operating Properly (COP) Reset
8.4.2.3 Illegal Opcode Reset
8.4.2.4 Illegal Address Reset
MC68HC08AZ60A — Rev 0.0
MOTOROLA
An input to the SIM is reserved for the COP reset signal. The overflow of
the COP counter causes an internal reset and sets the COP bit in the
SIM reset status register (SRSR). The SIM actively pulls down the RST
pin for all internal reset sources.
To prevent a COP module timeout, a value (any value) should be written
to location $FFFF. Writing to location $FFFF clears the COP counter and
bits 12 through 4 of the SIM counter. The SIM counter output, which
occurs at least every 2
counter. The COP should be serviced as soon as possible out of reset
to guarantee the maximum amount of time before the first timeout.
The COP module is disabled if the RST pin or the IRQ pin is held at
V
disabled only through combinational logic conditioned with the high
voltage signal on the RST or the IRQ pin. This prevents the COP from
becoming disabled as a result of external noise. During a break state,
V
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the SIM reset status register
(SRSR) and causes a reset.
If the STOP enable bit, STOP, in the mask option register is logic ‘0’, the
SIM treats the STOP instruction as an illegal opcode and causes an
illegal opcode reset. The SIM actively pulls down the RST pin for all
internal reset sources.
An opcode fetch from an unmapped address generates an illegal
address reset. The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the SIM reset status register SRSR) and
resetting the MCU. A data fetch from an unmapped address does not
generate a reset. The SIM actively pulls down the RST pin for all internal
reset sources.
DD
DD
+ V
+ V
HI
HI
while the MCU is in monitor mode. The COP module can be
on the RST pin disables the COP module.
System Integration Module (SIM)
13
– 2
4
CGMXCLK cycles, drives the COP
System Integration Module (SIM)
Reset and System Initialization
Advance Information
125