MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 196

• Manufacturer Part Number: MC68HC08AZ60ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Low Voltage Inhibit (LVI)
14.3 Features
14.4 Functional Description
Advance Information
196
NOTE:
Features of the LVI module include the following:
If a low voltage interrupt (LVI) occurs during programming of EEPROM
memory, then adequate programming time may not have been allowed
to ensure the integrity and retention of the data. It is the responsibility of
the user to ensure that in the event of an LVI any addresses being
programmed receive specification programming conditions.
Figure 14-1
out of reset. The LVI module contains a bandgap reference circuit and
comparator. The LVI power bit, LVIPWR, enables the LVI to monitor V
voltage. The LVI reset bit, LVIRST, enables the LVI module to generate
a reset when V
that level for 9 or more consecutive CPU cycles.
Note that short V
responsibility to ensure a clean V
operating voltage range if normal microcontroller operation is to be
guaranteed.
LVISTOP enables the LVI module during stop mode. This will ensure
when the STOP instruction is implemented the LVI will continue to
monitor the voltage level on V
LVIPWR, LVIRST and LVISTOP are mask options. See
on page 167. Once an LVI reset occurs, the MCU remains in reset until
V
one CPU cycle to bring the MCU out of reset. The output of the
comparator controls the state of the LVIOUT flag in the LVI status
register (LVISR).
DD
•
•
•
rises above a voltage, LVI
Programmable LVI reset
Programmable power consumption
Digital filtering of VDD pin level
shows the structure of the LVI module. The LVI is enabled
Low Voltage Inhibit (LVI)
DD
falls below a voltage, LVI
DD
spikes may not trip the LVI. It is the user’s
DD
TRIPR
.
. V
DD
DD
signal within the specified
must be above LVI
TRIPF
, and remains at or below
MC68HC08AZ60A — Rev 0.0
Mask Options
TRIPR
MOTOROLA
for only
DD