MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 270

• Manufacturer Part Number: MC68HC08AZ60ACFU
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Serial Peripheral Interface (SPI)
17.12 I/O Signals
Advance Information
270
To protect status bits during the break state, a ‘0’ should be written to the
BCFE bit. With BCFE at ‘0’ (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a two-step read/write clearing procedure. If software
does the first step on such a bit before the break, the bit cannot change
during the break state as long as BCFE is a ‘0’. After the break, the
second step clears the status bit.
Since the SPTE bit cannot be cleared during a break with the BCFE bit
cleared, a write to the data register in break mode will not initiate a
transmission, nor will this data be transferred into the shift register.
Therefore, a write to the SPDR in break mode with the BCFE bit cleared
has no effect.
The SPI module has five I/O pins and shares four of them with a parallel
I/O port.
The SPI has limited inter-integrated circuit (I
software support) as a master in a single-master environment. To
communicate with I
when the SPWOM bit in the SPI control register is set. In I
communication, the MOSI and MISO pins are connected to a
bidirectional pin from the I
V
DD
•
•
•
•
•
.
MISO — data received
MOSI — data transmitted
SPSCK — serial clock
SS — slave select
V
SS
Serial Peripheral Interface (SPI)
— clock ground
2
C peripherals, MOSI becomes an open-drain output
2
C peripheral and through a pullup resistor to
2
C) capability (requiring
MC68HC08AZ60A — Rev 0.0
2
C
MOTOROLA