MC68HC08AZ60ACFU MOTOROLA [Motorola, Inc], MC68HC08AZ60ACFU Datasheet - Page 121
MC68HC08AZ60ACFU
Manufacturer Part Number
MC68HC08AZ60ACFU
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC08AZ60ACFU.pdf
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8.3.1 BusTiming
8.3.2 Clock Start-Up From POR or LVI Reset
8.3.3 Clocks in STOP and WAIT Mode
8.4 Reset and System Initialization
MC68HC08AZ60A — Rev 0.0
MOTOROLA
In user mode, the internal bus frequency is either the crystal oscillator
output (CGMXCLK) divided by four or the PLL output (CGMVCLK)
divided by four. See Clock Generator Module (CGM).
When the power-on reset module or the low-voltage inhibit module
generates a reset, the clocks to the CPU and peripherals are inactive
and held in an inactive phase until after the 4096 CGMXCLK cycle POR
timeout has been completed. The RST pin is driven low by the SIM
during this entire period. The bus clocks start upon completion of the
timeout.
Upon exit from STOP mode (by an interrupt, break, or reset), the SIM
allows CGMXCLK to clock the SIM counter. The CPU and peripheral
clocks do not become active until after the STOP delay timeout. This
timeout is selectable as 4096 or 32 CGMXCLK cycles. See STOP
mode.
In WAIT mode, the CPU clocks are inactive. The SIM also produces two
sets of clocks for other modules. Refer to the WAIT mode subsection of
each module to see if the module is active or inactive in WAIT mode.
Some modules can be programmed to be active in WAIT mode.
The MCU has the following reset sources:
•
•
•
•
Power-on reset module (POR)
External reset pin (RST)
Computer operating properly module (COP)
Low-voltage inhibit module (LVI)
System Integration Module (SIM)
System Integration Module (SIM)
Reset and System Initialization
Advance Information
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