HD6413308 Hitachi Semiconductor, HD6413308 Datasheet - Page 159

• Manufacturer Part Number: HD6413308
• Description: Hitachi Single-Chip MicroComputer
• Manufacturer: Hitachi Semiconductor

Figure 6-15 shows how input capture operates when ICRA and ICRC are used in buffer mode and
IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDGA = 1 and
IEDGC = 0), so that input capture is performed on both the rising and falling edges of FTIA.
In this mode, FTIC does not cause the FRC contents to be copied to ICRC. However, input capture
flag C still sets on the edge of FTIC selected by IEDGC, and if the interrupt enable bit (ICICE) is
set, a CPU interrupt is requested.
The situation when ICRB and ICRD are used in buffer mode is similar.
(2) Timing of Input Capture Flag (ICF) Setting: The input capture flag ICFx (x = A, B, C, D) is
set to “1” by the internal input capture signal. Figure 6-16 shows the timing of this operation.
FTIA
Internal input
capture signal
FRC
ICRA
ICRC
Ø
Ø
Internal input
capture signal
ICF
FRC
ICR
Figure 6-15. Buffered Input Capture with Both Edges Selected
n
n
Figure 6-16. Setting of Input Capture Flag
n + 1
144
N
N
n
N
N
n
N + 1