HD6413308 Hitachi Semiconductor, HD6413308 Datasheet - Page 339

• Manufacturer Part Number: HD6413308
• Description: Hitachi Single-Chip MicroComputer
• Manufacturer: Hitachi Semiconductor

SSR—Serial Status Register
Bit
Initial value
Read/Write R/(W)* R/(W)*
* Software can write a “0” in bits 7 to 3 to clear the flags, but cannot write a “1” in these bits.
RDR—Receive Data Register
Bit
Initial value
Read/Write
TDRE
Transmit Data Register Empty
0 Cleared when CPU reads TDRE = “1,” then writes “0” in TDRE
1 Set when:
R
0
7
1
7
1. Data is transferred from TDR to TSR.
2. TE is cleared while TDRE = "0."
RDRF
1 Set when one character is received normally and transferred from
Receive Data Register Full
0 Cleared when CPU reads RDRF = “1,” then writes “0” in RDRF.
R
6
0
6
0
RSR to RDR.
Overrun Error
0 Cleared when CPU reads ORER = “1,” then writes “0” in ORER.
1 Set when an overrun error occurs (next data is completely
received while RDRF bit is set to “1”).
R/(W)*
ORER
0 Cleared when CPU reads FER = “1,” then writes “0” in FER.
Framing Error
1 Set when a framing error occurs (stop bit is “0”).
R
5
0
5
0
R/(W)* R/(W)*
FER
Receive data
Parity Error
0 Cleared when CPU reads PER = “1,” then
1 Set when a parity error occurs (parity of receive
R
4
0
4
0
331
writes “0” in PER.
data does not match parity selected by O/E bit).
PER
R
3
0
3
0
H’FFDD
H’FFDC
—
—
R
1
2
0
2
—
—
R
1
0
1
1
SCI
SCI
—
—
R
0
1
0
0