S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 125

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

1. Read: Anytime.
2.3.29
Freescale Semiconductor
Function
Address 0x0248
Write: Anytime.
Altern.
Field
Reset
PTS
PTS
PTS
PTS
PTS
PTS
7
6
5
4
3
2
W
R
Port S general purpose input/output data—Data Register
Port S pin 7 is associated with the SS signal of the SPI0 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port S general purpose input/output data—Data Register
Port S pin 6 is associated with the SCK signal of the SPI0 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port S general purpose input/output data—Data Register
Port S pin 5 is associated with the MOSI signal of the SPI0 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port S general purpose input/output data—Data Register
Port S pin 4 is associated with the MISO signal of the SPI0 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port S general purpose input/output data—Data Register
Port S pin 3 is associated with the TXD signal of the SCI1 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
Port S general purpose input/output data—Data Register
Port S bits 2 is associated with the RXD signal of the SCI1 module.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bit of this pin is set to 1, a read returns the value of the port register, otherwise the
buffered pin input state is read.
PTS7
Port S Data Register (PTS)
SS0
0
7
PTST6
SCK0
0
6
Table 2-26. PTS Register Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
Figure 2-27. Port S Data Register (PTS)
MOSI0
PTS5
0
5
MISO0
PTS4
0
4
Description
TXD1
PTS3
3
0
Chapter 2 Port Integration Module (S12XEPIMV1)
RXD1
PTS2
0
2
Access: User read/write
TXD0
PTS1
0
1
RXD0
PTS0
0
0
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