S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 584

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Chapter 15 Inter-Integrated Circuit (IICV3) Block Description
The equation used to generate the divider values from the IBFD bits is:
The SDA hold delay is equal to the CPU clock period multiplied by the SDA Hold value shown in
Table
The equation for SCL Hold values to generate the start and stop conditions from the IBFD bits is:
584
MUL=1
SCL
SDA
15-7. The equation used to generate the SDA Hold value from the IBFD bits is:
SCL Divider = MUL x {2 x (scl2tap + [(SCL_Tap -1) x tap2tap] + 2)}
SDA Hold = MUL x {scl2tap + [(SDA_Tap - 1) x tap2tap] + 3}
SCL Hold(start) = MUL x [scl2start + (SCL_Tap - 1) x tap2tap]
SCL Hold(stop) = MUL x [scl2stop + (SCL_Tap - 1) x tap2tap]
IBC[7:0]
(hex)
00
01
02
03
04
05
A master SCL divider period can be prolonged at higher internal bus
frequencies. This happens when the internal bus cycle length becomes equal
to a pad delay. The SCL input is used for clock arbitration of multiple
masters. Thus after each SCL edge is internally driven an extra bus period
is counted before the pad level is attained, allowing the next toggle. This has
the effect of extending the SCL Divider values in
and IBC[7:0] = 0x00 to 0x0F.
START condition
Table 15-7. IIC Divider and Hold Values (Sheet 1 of 6)
SCL Divider
(clocks)
MC9S12XE-Family Reference Manual Rev. 1.25
20
22
24
26
28
30
Figure 15-5. SCL Divider and SDA Hold
SCL Hold(start)
NOTE
SDA Hold
(clocks)
7
7
8
8
9
9
Table 15-7
STOP condition
SCL Hold
(start)
10
11
6
7
8
9
for MUL=1
Freescale Semiconductor
SCL Hold(stop)
SCL Hold
(stop)
11
12
13
14
15
16