S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 801

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Read: Anytime
Write: Anytime.
22.3.2.10 Timer Interrupt Enable Register (TIE)
Read: Anytime
Write: Anytime.
Freescale Semiconductor
Module Base + 0x000C
EDGnB
EDGnA
C7I:C0I
Reset
Field
Field
7:0
7:0
W
R
Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector
circuits.
Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in
the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set,
the corresponding flag is enabled to cause a interrupt.
C7I
0
7
C6I
0
6
EDGnB
Figure 22-18. Timer Interrupt Enable Register (TIE)
Table 22-12. Edge Detector Circuit Configuration
0
0
1
1
Table 22-11. TCTL3/TCTL4 Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
Table 22-13. TIE Field Descriptions
C5I
EDGnA
0
5
0
1
0
1
Capture on any edge (rising or falling)
C4I
0
4
Capture on falling edges only
Capture on rising edges only
Description
Description
Capture disabled
Configuration
Chapter 22 Timer Module (TIM16B8CV2) Block Description
C3I
0
3
C2I
0
2
C1I
0
1
C0I
0
0
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