S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 504

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S912XET256J2VAGR

Manufacturer Part Number
S912XET256J2VAGR
Description
16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S912XET256J2VAGR

Core
HCS12X
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
256 KB
Data Ram Size
16 KB
On-chip Adc
Yes
Package / Case
LQFP
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
24
Interface Type
CAN, SCI, SPI
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
119
Number Of Timers
25
Program Memory Type
Flash
Supply Voltage - Max
1.98 V, 2.9 V, 5.5 V
Supply Voltage - Min
1.72 V, 2.7 V, 3.13 V
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1)
13.1.2
13.1.2.1
There is software programmable selection between performing single or continuous conversion on a
single channel or multiple channels.
13.1.2.2
504
Stop Mode
— ICLKSTP=0 (in ATDCTL2 register)
— ICLKSTP=1 (in ATDCTL2 register)
Wait Mode
ADC12B16C behaves same in Run and Wait Mode. For reduced power consumption continuos
conversions should be aborted before entering Wait mode.
Freeze Mode
In Freeze Mode the ADC12B16C will either continue or finish or stop converting according to the
FRZ1 and FRZ0 bits. This is useful for debugging and emulation.
Entering Stop Mode aborts any conversion sequence in progress and if a sequence was aborted
restarts it after exiting stop mode. This has the same effect/consequences as starting a
conversion sequence with write to ATDCTL5. So after exiting from stop mode with a
previously aborted sequence all flags are cleared etc.
A/D conversion sequence seamless continues in Stop Mode based on the internally generated
clock ICLK as ATD clock. For conversions during transition from Run to Stop Mode or vice
versa the result is not written to the results register, no CCF flag is set and no compare is done.
When converting in Stop Mode (ICLKSTP=1) an ATD Stop Recovery time
required to switch back to bus clock based ATDCLK when leaving Stop Mode. Do not access
ATD registers during
Modes of Operation
Conversion Modes
MCU Operating Modes
MC9S12XE-Family Reference Manual Rev. 1.25
this time
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Freescale Semiconductor
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ATDSTPRCV
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